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hm62w1664hb series 1 m high speed sram (64-kword 16-bit) ade-203-415b (z) rev. 2.0 nov. 1997 description the hm62w1664hb is an asynchronous high speed static ram organized as 64-kword 16-bit. it realize high speed access time (25/30 ns) with employing 0.8 m m cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. the hm62w1664hb is packaged in 400-mil 44-pin soj for high density surface mounting. features single 3.3 v supply (3.3 v 0.3v) access time: 25/30 ns (max) completely static memory ? no clock or timing strobe required equal access and cycle times directly lv-ttl compatible ? all inputs and outputs 400-mil 44-pin soj package center v cc and v ss type pinout ordering information type no. access time package HM62W1664HBJP-25 hm62w1664hbjp-30 25 ns 30 ns 400-mil 44-pin plastic soj (cp-44d) hm62w1664hbljp-25 hm62w1664hbljp-30 25 ns 30 ns
hm62w1664hb series 2 pin arrangement a4 a3 a2 a1 a0 cs i/o1 i/o2 i/o3 i/o4 v cc v ss i/o5 i/o6 i/o7 i/o8 we a15 a14 a13 a12 nc (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a5 a6 a7 oe ub lb i/o16 i/o15 i/o14 i/o13 v ss v cc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 a11 nc hm62w1664hbjp/hbljp series pin description pin name function a0 C a15 address input i/o1 C i/o16 data input/output cs chip select oe output enable we write enable ub upper byte select lb lower byte select v cc power supply v ss ground nc no connection
hm62w1664hb series 3 block diagram i/o1 we input data control memory matrix 256 rows 256 columns 16 bit (1,048,576 bits) row decoder oe cs cs cs v cc v ss cs lb ub i/o16 i/o9 i/o8 . . . . . . a3 a2 a1 a0 a7 a6 a5 a4 a12 a11 a10 a15 a14 a13 a9 a8 column i/o column decoder (lsb) (msb) (lsb) (msb) function table cs oe we lb ub mode v cc current i/o1Ci/o8 i/o9Ci/o16 ref. cycle h standby i sb , i sb1 high-z high-z lhh output disable i cc high-z high-z l l h l l read i cc output output read cycle l l h l h lower byte read i cc output high-z read cycle l l h h l upper byte read i cc high-z output read cycle l l hhh i cc high-z high-z l l l l write i cc input input write cycle l l l h lower byte write i cc input high-z write cycle l l h l upper byte write i cc high-z input write cycle l l hh i cc high-z high-z note: : h or l
hm62w1664hb series 4 absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc C0.5 to +4.6 v voltage on any pin relative to v ss v t C0.5* 1 to v cc + 0.5 v power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c storage temperature under bias tbias C10 to +85 c notes: 1. v t (min) = C2.5 v for pulse width (under shoot) 10 ns recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc * 2 3.0 3.3 3.6 v v ss * 3 000v input voltage v ih 2.0 v cc + 0.3 v v il C0.3* 1 0.8 v notes: 1. C2.0 v for pulse width (under shoot) 10 ns 2. the supply voltage with all v cc pins must be on the same level. 3. the supply voltage with all v ss pins must be on the same level.
hm62w1664hb series 5 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol min typ* 1 max unit test conditions input leakage current |i li |2 m a vin = v ss to v cc output leakage current* 1 |i lo |2 m a vin = v ss to v cc operating power supply current 25 ns cycle i cc 100 ma cs = v il , iout = 0 ma other inputs = v ih /v il 30 ns cycle i cc 90 standby power supply current 25 ns cycle i sb 40ma cs = v ih , other inputs = v ih /v il 30 ns cycle i sb 35 i sb1 1 mav cc 3 cs 3 v cc C 0.2 v, (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc C 0.2 v * 2 * 2 0.15* 2 output voltage v ol 0.2 v i ol = 0.1 ma 0.4 v i ol = 2 ma v oh v cc C 0.2 v i oh = C0.1 ma 2.4 v i oh = C2 ma note: 1. typical values are at v cc = 3.3 v, ta = +25 c and not guaranteed. 2. this characteristics is guaranteed only for l-version. capacitance (ta = 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 6 pf vin = 0 v input/output capacitance* 1 c i/o 8 pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62w1664hb series 6 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, unless otherwise noted.) test conditions input pulse levels: 2.4 v/0.4 v input rise and fall time: 3 ns input and output timing reference levels: 1.4 v output load: see figures (including scope and jig) dout 500 w 30 pf output load (a) dout 500 w 5 pf 1.4v 1.4v output load (b) (for t clz , t olz , t lblz , t ublz , t chz , t ohz , t lbhz , t ubhz , t whz , and t ow ) read cycle hm62w1664hb -25 hm62w1664hb -30 parameter symbol min max min max unit notes read cycle time t rc 25 30 ns address access time t aa 25 30 ns chip select access time t acs 25 30 ns output enable to output valid t oe 15 15 ns byte select to output valid t lb , t ub 15 15 ns output hold from address change t oh 55ns chip select to output in low-z t clz 55ns1 output enable to output in low-z t olz 11ns1 byte select to output in low-z t lblz , t ublz 11ns1 chip deselect to output in high-z t chz 12 12 ns 1 output disable to output in high-z t ohz 12 12 ns 1 byte deselect to output in high-z t lbhz , t ubhz 12 12 ns 1
hm62w1664hb series 7 write cycle hm62w1664hb -25 hm62w1664hb -30 parameter symbol min max min max unit notes write cycle time t wc 25 30 ns address valid to end of write t aw 20 20 ns chip select to end of write t cw 20 20 ns 8 write pulse width t wp 20 20 ns 7 byte select to end of write t lbw , t ubw 20 20 ns 9, 10 address setup time t as 00ns5 write recovery time t wr 00ns6 data to write time overlap t dw 15 15 ns data hold from write time t dh 00ns write disable to output in low-z t ow 55ns1 output disable to output in high-z t ohz 12 12 ns 1 write enable to output in high-z t whz 12 12 ns 1 notes: 1. transition is measured 200 mv from steady voltage with load (b). this parameter is sampled and not 100% tested. 2. if the cs or lb or ub low transition occurs simultaneously with the we low transition or after the we transition, output remains a high impedance state. 3. we and/or cs must be high during address transition time. 4. if cs , oe , lb and ub are low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 5. t as is measured from the latest address transition to the latest of cs , we , lb or ub going low. 6. t wr is measured from the earliest of cs , we , lb or ub going high to the first address transition. 7. a write occurs during the overlap of low cs , low we and low lb or low ub . 8. t cw is measured from the later of cs going low to the end of write. 9. t lbw is measured from the later of lb going low to the end of write. 10. t ubw is measured from the later of ub going low to the end of write.
hm62w1664hb series 8 timing waveforms read timing waveform (1) ( we = v ih ) t aa t acs t oe t lb t ub t lblz t ublz t olz t clz t oh t chz t ohz t lbhz t rc valid data address dout (upper byte) valid address high impedance valid data dout (lower byte) cs oe lb ub high impedance * 1 * 1 * 1 t ubhz * 1 * 1 * 1 * 1 * 1 * 4 * 4 * 4 * 4
hm62w1664hb series 9 read timing waveform (2) ( we = v ih , lb = v il , ub , = v il ) t aa t acs t rc t oe t clz valid data address cs dout (lower/upper byte) valid address high impedance t ohz oe t oh t chz t olz * 1 * 1 * 1 * 1 * 4 * 4
hm62w1664hb series 10 write timing waveform (1) ( lb , ub controlled) address we * 3 t wc t aw t as t wr t wp t whz t olz t ow t ohz t cw t lbw t ubw t dh t dw t dh t dw valid address valid data valid data cs * 3 oe lb ub dout (lower byte) dout (upper byte) din (lower byte) din (upper byte) high impedance high impedance
hm62w1664hb series 11 write timing waveform (2) ( we controlled) address we * 3 t wc t aw t as t wr t wp t whz t olz t ow t ohz t cw t lbw t ubw t dh t dw valid address valid data cs * 3 oe lb , ub dout (lower/upper byte) din (lower/upper byte) high impedance * 2
hm62w1664hb series 12 write timing waveform (3) ( cs controlled) address cs * 3 t wc t aw t as t wr t wp t whz t olz t ow t ohz t cw t lbw t ubw t dh t dw valid address valid data we * 3 oe lb , ub dout (lower/upper byte) din (lower/upper byte) high impedance * 2 * 4
hm62w1664hb series 13 low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for l-version. parameter symbol min typ* 1 max unit test conditions v cc for data retention v dr 2.0 v v cc 3 cs 3 v cc C 0.2 v, (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc C 0.2 v data retention current i ccdr 2 80 m av cc = 3 v v cc 3 cs 3 v cc C 0.2 v, (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc C 0.2 v chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r 5 ms note: 1. typical values are at v cc = 3.0 v, ta = 25 c, and not guaranteed. low v cc data retention timing waveform v cc 3.0 v 2.0 v 0 v cs t cdr t r v cc 3 cs 3 v cc ?0.2 v dr v data retention mode
hm62w1664hb series 14 package dimensions hm62w1664hbjp/hbljp series (cp-44d) 28.33 28.90 max 44 23 122 10.16 0.13 11.18 0.13 3.50 0.26 0.10 0.43 0.10 9.40 0.25 2.65 0.12 0.74 1.30 max 1.27 0.80 +0.25 ?.17 hitachi code jedec eiaj weight (reference value) cp-44d conforms 1.8 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension
hm62w1664hb series 15 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm62w1664hb series 16 revision record rev. date contents of modification drawn by approved by 0.0 aug. 3, 1995 initial issue t. nojiri k. yoshizaki 0.1 jul. 18, 1996 change of format change of block diagram function table addition of mode parameter recommended dc operating conditions change of note 2. addition of note 3. dc characteristics addition of note 2 ac characteristics change order of notes t oe (max) : 12/15 ns to 15/15 ns t aw (min) : 15/20 ns to 20/20 ns t cw (min) : 15/20 ns to 20/20 ns t wp (min) : 15/20 ns to 20/20 ns t lbw , t ubw (min) : 15/20 ns to 20/20 ns t dw (min) : 12/15 ns to 15/15 ns t whz (max) : 10/10 ns to 12/12 ns addition of t oe (write cycle) change of timing waveform addition of read timing waveform (2) y. saito a. ide 1.0 dec. 25, 1996 deletion of preliminary y. saitoh a. ide 2.0 nov. 1997 change of subtitle

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